Articles de revues:
[1] ZAKI, M., DENMAN, W., TAHAR, S., BOIS, G., «Integrating Abstraction Techniques for the Formal Verification of Analog Designs», Journal of Aerospace Computing, Information, and Communication (JCAIC), To appear in 2009.
[2] ZAKI, M., TAHAR, S., BOIS, G., « Formal Verification of Analog and Mixed Signal Designs: A Survey », Microelectronics Journal, ELSEVIER, June 2006, pp. 281-284,
ISBN: 1-4244-0416-9
[3] BEUCHER N., BELANGER N., SAVARIA Y., BOIS G., «Motion Compensated Frame Rate Conversion Using Specialized Instruction Set Processor», Journal of Signal Processing Systems, SpringerLink, May 2008 (www.springerlink.com/content/48255391100x1531/).
[4] MAHONEY, P., SAVARIA, Y., BOIS, G., PLANTE, P., «Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hasching Memories», Transactions on High-Performance Embedded Architecture and Compilers (HiPEAC), Vol.2, 2008.
[5] ZAKI, M., TAHAR, S., BOIS, G., «Qualitative Abstraction based Verification for Analog Circuits», Revue des Nouvelles Technologies de l'information, RNTI-SM-1, Edition Cepadues, Dec. 2007, pp. 147-158.
[6] CHEVALIER, J., DE NANCLAS, FILION L., BENNY O., RONDONNEAU, M., BOIS, G., ABOULHAMID, E.-M., "A SystemC Refinement Methodology for Embedded Software," Design & Test of Computers, IEEE, vol. 23, no. 2, pp. 148-158, 2006.
[7] DUBOIS, M., BOIS, G., SAVARIA, Y., «A Double Profiling Methodology for a Video Processing Platform», WSEAS TRANSACTIONS from WSEAS Conferences, Canary Islands, Spain, Dec., 2004, issue 6, vol. 3, pp. 1802-1807.
[8] CYR, G., BOIS, G. ABOULHAMID, «Generation of processor interface for SoC using VSIA recommendations», IEE Proc. - Computers and Digital Techniques, Vol. 151, No. 5, pp. 367-376, sept. 2004, pp. 367-376.
[9] BEAUDIN, S., MARCEAU, R. J., BOIS, G., SAVARIA, Y., KANDIL, N., «An Economic Parallel Processing Technology for Faster than Real-Time Transient Stability Simulation», European Transactions on Electrical Power, March-April 2003, pp. 105-112.
6 autres avant 2003
Chapitres de livres:
[10] BOIS, G., MOSS, L., FILION, L., FONTAINE, S., «Experiences based on a virtual platform», Chap. 9 of ESL Models and their Application: Electronic System Level Design and Verification in Practice, Ed. Brian Bailey and Grant Martin, Springer, Chap. 9, To appear in 2010.
[11] CHEVALIER J., BENNY O., RONDONNEAU, M., BOIS, G., ABOULHAMID, E.-M., BOYER, J.-F., «SPACE: A Hardware/Software SystemC modeling platform including an RTOS », Book chapter Languages for System Specification and Verification, Ed. Christoph Grimm, serie CHDL of Kluwer Academic Publishers (best papers of FDL03), ISBN 1-4020-7990-7, June 2004.(NSERC ind & strat.)
[12] BOIS G., FILION L., TSIKHANOVICH A., ABOULHAMID E.M., «Modélisation, raffinement et techniques de programmation orientée objet avec SystemC », Chap. 6 of La spécification et la validation des systèmes hétérogènes embarqués, A.A. JERRAYA et G. NICOLESCU (ed.), Hermes, ISBN 2-7462-0820-2, 2004, pp. 171-207.
[13] CHAREST, L., ABOULHAMID, M., BOIS, G., «Applying multi-paradigm and patterns approaches to hardware/software design and reuse», Chap. 11 of Patterns and Skeletons for Parallel and Distributed Computing, RABHI, F. E. (ed.), Springer Verlag, 2003, pp.297-325. ISBN 1-85233-506-8.
Conférences:
[14] LE BEUX, S., NICOLESCU, G., BOIS, G, BOUCHEBABA, Y., LANGEVIN M., and PAULIN, P., « Optimizing configuration and application mapping for MPSoC architectures». In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2009), San Francisco, CA, July 2009.
[15] LANG, N., CANTIN, M.-A., BOIS, G., «Assisted creation and refinement of transactional level specifications based on IP-XACT», IP Based Electronics System Conference & Exhibition, Grenoble, December 2008
[16] TSIKHANOVICH, A. ABOULHAMID, E.M., BOIS, « Temporal Constraints Analysis for Timing Verification of Systems», IEEE 20th International Conference on Microelectronics, Sharjah, UAE, December 2008.
[17] FONTAINE, S., GOYETTE, S., LANGLOIS, J.M., BOIS, G., «Acceleration of a 3D Target Tracking Algorithm Using an Application Specific Instruction set Processor », IEEE 25th International Conference On Computer Design, CA, October 2008.
[18] FONTAINE, S., FILION, L., BOIS, G., «Exploring ISS Abstractions for Embedded Software Design», 11th EUROMICRO CONFERENCE on DIGITAL SYSTEM DESIGN Architectures, Italia, September 2008.
[19] MOSS, L., CANTIN, M.-A., BOIS, G., ABOULHAMID, E.-M., « Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology», 19th IEEE/IFIP
International Symposium on Rapid System Prototyping, Monterey, CA, June 2008.
[20] DONG Z. J., ZAKI M., SAMMANE, AL-SAMMANE G, TAHAR S., BOIS G., «Checking Properties of PLL Designs using Run-time Verification», 19th Intern. Conference on Microelectronics, Cairo, Egypt, December 2007.
[21] BEUCHER N., BELANGER N., SAVARIA Y., BOIS G., « A Methodology to Evaluate the Energy Efficiency of Application Specific Processors», 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, December 2007.
[22] HADJIAT, K., ST-PIERRE, F., M., BOIS, G., SAVARIA, Y., PAULIN, P., « An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept », 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, December 2007.
[23] TSIKHANOVICH, A. ABOULHAMID, E.M., BOIS, «Communication Structure Refinement Using Temporal Constraints Analysis», 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco, December 2007.
[24] ZAKI, M., AL-SAMMANE, G., TAHAR, S., BOIS, G., «Combining Symbolic Simulation and Interval Arithmetics for the Verification of AMS Designs», Formal Methods In Computer Aided Design, Austin, TX, November 2007.
[25] AL-SAMMANE, G., ZAKI, M., TAHAR, S., BOIS, G., «Constraint based Verification, Formal Verification, Interval Analysis, Symbolic Methods, Delta Sigma Modulators », Proc. IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada, August 2007.
[26] DONG, Z. J., ZAKI, M., AL-SAMMANE, G., TAHAR, S., BOIS, G., «Run-Time Verification Using the VHDL-AMS Simulation Environment», Proc. IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada, August 2007.
[27] TSIKHANOVICH, A. ABOULHAMID, E.M., BOIS, «Timing Specification in Transaction Level Modeling of Hardware/Software Systems», Proc. IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada, August 2007.
[28] ZAKI, M., TAHAR, S., BOIS, G., «A Symbolic Approach for the Safety Verification of Continuous Systems», Real Time System and Adaptive Application Workshop (RTSAA' 07) at International Conference on Computational Science, Beijing, China, May 2007.
[29] FILION, L., CANTIN M.-A., MOSS L., ABOULHAMID E.-M., BOIS G. «Space Codesign : A SystemC Framework for Fast Exploration of Hardware/Software Systems», Design and Verification Conference (DVCON’07), San Jose, Feb. 2007.
[30] MOSS, L., FONTAINE, S., DE NANCLAS, M., FILION, L., ABOULHAMID E.-M., BOIS G., «Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support», Design Automation and Test in Europe Conf., Nice, April 2007.
[31] ZAKI, M., TAHAR, S., BOIS, G., «Abstraction Based Verification of Analog Circuits Using Computer Algebra and Constraint Solving», Proc. Of International Workshop on Symbolic Methods and Applications to Circuit Design, Italia, October 2006.
[32] BEUCHER N., BELANGER N., SAVARIA Y., BOIS G., «Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor », IEEE 2006 Workshop on Signal Processing Systems, Banff, October 2006.
[33] PROVOST, S., LAVIGUEUR, B., BOIS, G., NICOLESCU, G., « Integration of Configurable Processors in a Multiprocessor platform », IEEE SOCC, Atlanta, September 2006, pp. 221-224. (NSERC strat.)
[34] ZAKI, M., TAHAR, S., BOIS, G., «Formal Verification of Analog and Mixed Signal Designs: Survey and Comparison» Proc. IEEE Northeast Workshop on Circuits and Systems, Gatineau, Quebec, Canada, June 2006.
[35] DESLAURIERS, F., LANGEVIN, M., BOIS, G., SAVARIA, Y., PAULIN, P., «RoC: A Scalable Network on Chip Based on the Token Ring Concept», Proc. of Northeast Workshop on Circuits and Systems, Gatineau, Canada, June 2006.
[36] ZAKI, M., TAHAR, S., BOIS, G., «A Practical Approach for Monitoring Analog Circuits», Proc. ACM 16th Great Lakes Symposium on VLSI, Philadelphia, Pennsylvania, USA, April 2006, ACM Publications.
[37] ZAKI, M., TAHAR, S., BOIS, G., «On the formal Analysis of Analog Systems using Interval Abstraction», Proc. of the Verification and Theorem Proving for Continuous Systems Workshop, Oxford UK, August 2005.
[38] TSIKHANOVICH, A. ABOULHAMID, E.M., BOIS, G., "A methodology for HW/SW specification and simulation at multiple levels of abstraction," Proc. Fifth International Workshop on System-on-Chip for Real-Time Applications, 20-24 July, 2005, pp. 24-29.
[39] MAHONEY, P., SAVARIA, Y., BOIS, G., PLANTE, P., « Parallel Hashing Memories: an Alternative to Content Adressable Memories », Proc. of Northeast Workshop on Circuits and Systems, Montréal, Canada, June 2005, pp. 223-226
[40] THIBEAULT, J.-F., HUBIN, M., DESLAURIERS, F., SAMSON, P., BOIS, G., «A Reprogrammable SoC Design for a Real-Time Control Application», Proc. of Microelectronic Systems Educatution Conf., Anaheim, CA, USA, June 2005, pp. 73-74.
[41] DUBOIS, M., SAVARIA, Y., BOIS, G., «A Generic AHB Bus for Implementing High-Speed Locally Synchronous Islands», », Proc. of the IEEE SoutheastCon, Fort Lauderdale, USA, April 2005, pp.11-16.
[42] CHEVALIER, J., DE NANCLAS, M., BOIS, G., ABOULHAMID E.M, «SPACE: SystemC Partitioning of Architectures for Co-design of real-time Embedded systems», 2nd North American SystemC User’s Group, SanJose, USA, Sept. 2004, http://www.nascug.org/.
[43] CHAREST, L., ABOULHAMID, M., BOIS, G., «Using Design Patterns for Type Unification and Introspection in SystemC », Proc. of the International Workshop on System-on-Chip for Real-Time Applications, Banff, July 2004. (CD)
[44] LAPALME, J., ABOULHAMID E.M., NICOLESCU, G., CHAREST, L., DAVID, J.-P., BOYER, F., BOIS G., «ESys.NET: A New Solution for Embedded Systems Modeling and Simulation», ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems, Washington, DC, June 11-13, 2004, pp. 16-20.
[45] QUINN D., LAVIGUEUR B., BOIS G., ABOULHAMID M., « A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors», Proc. of Design Automation and Test in Europe 2004, Paris, 2004, pp. 364 - 369.
[46] LAPALME, J., ABOULHAMID E.M., NICOLESCU, G., CHAREST, L., DAVID, J.-P., BOYER, F., BOIS G., «Net Framework – A solution for the Next Generation Tools for System-Level Design ? », Proc. of Design Automation and Test in Europe 2004, Paris, 2004, pp. 732 – 733.
[47] BENNY O., RONDONNEAU, M., CHEVALIER J., BOIS, G., ABOULHAMID, E.-M., BOYER, J.-F., «SoC software refinement approach for a SystemC platform », Proc. of International Conference on Using Hardware Design and Verification Languages, San Jose, USA, February 2004. (CD)
[48] REGIMBAL S., SAVARIA, Y., BOIS, G., «Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models», Proc. of the International Workshop on System-on-Chip for Real-Time Applications, Banff, July 2004, pp. 87-92.
46 autres avant 2004
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