Articles publiés dans des revues


[1]    Daigneault, M.-A., David, J.P. “Fast Description and Synthesis of Control-Dominant Circuits”, accepted in Computers and Electrical Engineering, Elsevier, Feb 2014
[2]    Ould-Bachir T, David, J.P. Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. ACM Trans. Reconfigurable Technol. Syst. 6, 1, Article 1 (May 2013), 21 pages.
[3]    Ould Bachir T., Dufour C., Bélanger, J., Mahseredjian, J. and David, J.P., « A fully automated reconfigurable calculation engine dedicated to the  real-time simulation of high switching frequency power electronic circuits », Mathematics and Computers in Simulation, Volume 91, May 2013, pp. 167-177
[4]    Blanchette, H.F.; Ould-Bachir, T.; David, J.-P., "A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters," Industrial Electronics, IEEE Transactions on , vol.59, no.12, pp.4555-4567, Dec. 2012
[5]    Etienne Bergeron, Louis-David Perron, Marc Feeley, and Jean Pierre David, “Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation.” ACM Trans. Reconfigurable Technol. Syst. 4, 2, Article 12 (May 2011), 27 pages.
[6]    Daigneault, M.-A., David, J.P. , "A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration," Instrumentation and Measurement, IEEE Transactions on , vol.60, no.6, pp.2070-2079, June 2011.
[7]    David, J.P., Kalach, K., Tittley, N., "Hardware Complexity of Modular Multiplication and Exponentiation," Computers, IEEE Transactions on , vol.56, no.10, pp.1308-1319, Oct. 2007.


Actes de conférence avec comité de lecture


[8]    David, J.P., "Max-hashing fragments for large data sets detection," Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, pp.1-6, 9-11 Dec. 2013
[9]    Daigneault, M.A., David J.P. “Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)”. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA '13)
[10]    Daigneault, M.A., David, J.P. "High-Level Description and Synthesis of Floating-Point Accumulators on FPGA," Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on , vol., no., pp.206,209, 28-30 April 2013
[11]    Daigneault, M.A., David J.P. “Synchronized-Transfer-Level Design Methodology applied to Hardware Matrix Multiplication”, Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on , vol., no., pp.1,7, 5-7 Dec. 2012 
[12]    Daigneault, M.A., David J.P., “Raising the abstraction level of HDL for control-dominant applications”, Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on , vol., no., pp.515,518, 29-31 Aug. 2012.
[13]    Ould Bachir, T. and Dufour, C. and Bélanger, J. and Mahseredjian, J. and David, J.P. “Effective floating-point calculation engines intended for the FPGA-based HIL simulation”, IEEE International Symposium on Industrial Electronics (ISIE2012), Hangzhou China, May 28-31 2012.
[14]    Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David, « 2-level Configuration for FPGA: A New Design Methodology Based on a Computing Fabric », IEEE International Symposium on Circuits and Systems (ISCAS), Seoul Corea, May 2012.
[15]    Ould Bachir, T. and Dufour, C. and David, J.P. and Mahseredjian, J. and Bélanger, J. “Reconfigurable floating-point engines for the real-time simulation of PECs: a high-speed PMSM drive case study”, ELECTRIMACS, Paris, France, 6 pages, June 2011.
[16]    Ould Bachir, T. and Dufour, C. and David, J.P. and Mahseredjian, J. “Floating-point engines for the FPGA-based real-time simulation of power electronic circuits”, IPST, Delft, The Netherlands, 6 pages, June 2011.
[17]    Tarek Ould Bachir, Christian Dufour, Jean-Pierre David, Jean Bélanger, “Effective FPGA-based electric motor modeling with floating-point cores”, IECON/IEEE, pp. 829-834, Pheonix, Arizona, Nov. 2010.
[18]    Tarek Ould Bachir and Jean Pierre David, “FPGA-based real-time simulation of state-space models using floating-point cores”, EPE-PEMC 2010, Ohrid, Macedonia, 6-8 Sept. 2010, pp. S2-26 - S2-31.
[19]    Marc-André Daigneault, Jean-Pierre David, «A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA », NewCAS’2010, Montreal, QC, 20-23 June 2010, pp. 281 – 284.
[20]    Tarek Ould Bachir,and Jean Pierre David, “Performing Floating-Point Accumulation on a modern FPGA in Single and Double precision”, FCCM’2010, Charlotte, NC, 2-4 May 2010, pp. 105 – 108.
[21]    Marc-André Daigneault, Jean-Pierre David, «Towards 5ps Resolution TDC on a Dynamically Reconfigurable FPGA », FPGA’2010, Monterey, California, February 21-23, 2010. Poster.
[22]    Allard, M.; Grogan, P.; David, J.-P.; "A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA," Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on, pp.107-112, 9-11 Dec. 2009.
[23]    Bafumba-Lokilo, David; Savaria, Yvon; David, Jean-Pierre; "Generic array-based MPSoC architecture," Microsystems and Nanoelectronics Research Conference, 2009. MNRC 2009. 2nd ,  pp.128-131, 13-14 Oct. 2009.
[24]    Daigneault, M.-A.; Langlois, J.M.P.; David, J.P.; "Application Specific Instruction set processor specialized for block motion estimation," Computer Design, 2008. ICCD 2008. IEEE International Conference on , pp.266-271, 12-15 Oct. 2008.
[25]    Etienne Bergeron, Jean Pierre David, Marc Andre Daigneault, Marc Feeley, “Using Dynamic Reconfiguration to Implement High-Resolution Programmable Delays on an FPGA”, NEWCAS-TAISA’2008, Montréal, June 22-25 2008
[26]    David Bafumba, Yvon Savaria, Jean Pierre David, “Generic Crossbar Network on Chip for FPGA MPSoC”, NEWCAS-TAISA’2008, Montréal, June 22-25 2008
[27]    E. Bergeron, M. Feeley and J.P David “Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs”, CC2008 (membre de ETAPS), Budapest, April 2008. Aussi paru dans Lecture Notes in Computer Science, Compiler Construction, Springer Berlin / Heidelberg, Volume 4959/2008, ISBN 978-3-540-78790-7, 2008, pp 178-192
[28]    M. Hamine, Y. Audet, J.P. David,  “A Real Time Image Reconstruction Algorithm for an Integrated Fingerprint sensor”, accepté à MWSCAS/NEWCAS’2007, Montréal, 5-8 August 2007
[29]    E. Bergeron, M. Feeley, J.P. David,  “Toward on-Chip JIT Synthesis on XilinxII-Pro FPGAs”, MWSCAS/NEWCAS’2007, Montréal, 5-8 August 2007
[30]    X. Saint Mleux, M. Feely, J.P David, “SHard: a Scheme to Hardware Compiler”, Scheme and Functional Programming (affiliated with The 11th ACM SIGPLAN International Conference on Functional Programming (ICFP 2006), Portland, Oregon, September 2006
[31]    O. Brassard, M. Kastle, E. M. Aboulhamid, F. Rousseau, J.P. David, “Automatic Generation of Embedded Systems with .NET FrameworkBased Tools”,  Northeast Workshop on Circuits and Systems (NewCAS’2006), Gatineau, June 2006
[32]    X. Saint Mleux, M. Feely, J.P David, “A Scheme compiler for Hardware Dataflow Machines”, Languages, Compilers, and Tools for Embedded Systems (LCTES’2006), Ottawa, June 2006
[33]    E.Bergeron, X. Saint Mleux, M.Feeley, J.P. David, “High Level Synthesis for Data-Driven Applications”, Rapid Prototyping Systems (RSP’2005), Montréal, June 2005
[34]    K. Kalach, J.P. David, “Hardware Implementation of Large Number Multiplication by FFT with Modular Arithmetic”, Northeast Workshop on Circuits and Systems (NewCAS’2005), Montréal, June 2005
[35]    J.P. David, E. Bergeron, « An Intermediate Level HDL for System Level Design », Forum on specification and Design Languages (FDL), Lille, France, September 2004.
[36]    M.T. Zerarka, J.P. David, and E.M. Aboulhamid, « High Speed Emulation of Gene Regulatory Networks using FPGAs », IEEE International Midwest Symposium On Circuits and Systems (MWSCAS) Hiroshima, Japan, July 2004
[37]    J.P. David, E. Bergeron, « A Step towards Intelligent Translation from High-Level Design to RTL », International Workshop System-on-Chip for Real-Time Applications (IWSOC), Banff, Alberta, July 2004
[38]    E. Ogoubi, J.P David, « Automatic synthesis from high level ASM to VHDL: a case study », North East Workshop on Circuits and Systems (NewCAS), Montreal, Canada, June 2004
[39]    J. Lapalme, E. M. Aboulhamid, G. Nicolescu, L. Charest, F. R. Boyer, J. P. David, G. Bois , « ESys.Net: A New Solution for Embedded Systems Modeling and Simulation », June 2004, ACM SIGPLAN Notices , Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools, Volume 39 Issue 7 , also published in Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Washington, DC, June 2004
[40]    J. Lapalme, E. M. Aboulhamid, G. Nicolescu, L. Charest, F. R. Boyer, J. P. David, G. Bois , “.NET Framework – A solution for the next generation tools for system-level design ?”, Proceedings of the conference on Design Automation and Test in Europe (DATE’2004), Paris, France, February 2004
[41]    Li Ping Sun, El Mostapha Aboulhamid, and Jean-Pierre David, “Network on Chip Using a Reconfigurable Platform”, IEEE International Midwest Symposium On Circuits and Systems (MWSCAS) Cairo, Egypt, December 2003
[42]    J.P. David, « SystemC : Une perspective pour la conception simultanée logiciel/matériel de systèmes utilisant des ressources synchronisées par les données »,  accepté aux Journées Francophones Adéquation Algorithme Architecture (JFAAA’2002,Tunisia)
[43]    Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David and Jean-Didier Legat. ”A Cryptanalytic Time-Memory Tradeoff : First FPGA Implementation”. In Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications (FPL '02), Manfred Glesner, Peter Zipf, and Michel Renovell (Eds.). Springer-Verlag, London, UK, UK, 780-789.
[44]    François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David and Jean-Didier Legat. ”A FPGA Implementation of the Linear Cryptanalysis”. In Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications (FPL '02), Manfred Glesner, Peter Zipf, and Michel Renovell (Eds.). Springer-Verlag, London, UK, UK, 845-852.
[45]    J.P. David, Architecture synchronisée par les données pour système reconfigurable, Ph.D. Thesis, Université Catholique de Louvain, Laboratoire de Microélectronique, June 2002
[46]    J.P. David, J.D. Legat, "Architecture synchronisée par les données pour système reconfigurable", SympA'7 7ième Symposium en Architectures nouvelles de machines, Paris, 24-26 avril 2001, pp. 75-82.
[47]    J.P. David, J.D. Legat, P. Fisette, T. Postiau, "Implementation of Very Large Dataflow Graphs on a Reconfigurable Architecture for Robotic Application", Proc. of the 15th International Parallel & Distributed Processing Symposium, IPDPS'2001, 23-27 April 2001, San Francisco.
[48]    A.M. Trullemans, R. Ferreira, J.P. David, J.D. Legat, "A Multi-FPGA System for Prototyping Power Conscious Algorithms ", 15th Design of Circuits and Integrated Systems Conference (DCIS 2000), Montpellier, Nov. 21-24 2000, pp 41-46.
[49]    J.P. David, J.D. Legat, Invited Speaker, "A FPGA -Based Implementation of Adaptive Sound Filtering", Proc. Of CSSP'98, Mierlo (Netherlands), Nov. 26-27, 1998, pp. 107-111.
[50]    J.P. David, J.D. Legat "A Data-Flow Oriented Codesing for Reconfigurable Systems", IEEE Rapid System Prototyping (RSP'98), Leuven, June 1998, pp. 207-211.
[51]    J.P. David, J.D. Legat, "A multi-FPGA based coprocessor for digital signal processing" , IEEE Benelux Signal Processing Systems Symposium, Leuven, March 1998.
[52]    J.D. Legat, J.P. David, P. Desneux, "Programmable architectures for subband coding : FPGA -based systems versus dedicated VLSI chip", Proc. of IEEE 2nd IMACS Int. Multiconf., CESA'98 Computational Engineering in Systems Applications, Nabeul-Hammamet (Tunisia), April 1-4, 1998, pp. 301-305.
[53]    J.D. Legat, J.P. David, "Design of a multi-FPGA system for rapid prototyping experimentation, Proc. of the 2nd European workshop on Microelectronics Education, Noordwijkerhout (NL), 14-15/05/98. In : "Microelectronics Education", ed. T.J. Mouthaan and C. Salm, Kluwer Academic Publ., 1998, 0-7923-5107-X, pp. 231-234.
[54]    J.P. David, J.D. Legat, "A 400Kgates 8 Mbytes SRAM multi-FPGA PCI System", Int. Workshop on Logic and Architecture Synthesis, Grenoble, Dec. 1997, pp. 133-137.